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23A640/23K640
2.5
Read Status Register Instruction
The mode bits indicate the operating mode of the
( RDSR )
The Read Status Register instruction ( RDSR ) provides
access to the STATUS register. The STATUS register
may be read at any time. The STATUS register is
formatted as follows:
SRAM. The possible modes of operation are:
0 0 = Byte mode (default operation)
1 0 = Page mode
0 1 = Sequential mode
1 1 = Reserved
TABLE 2-2:
STATUS REGISTER
Write and read commands are shown in Figure 2-7 and
Figure 2-8.
7
W/R
6
W/R
5
–
4
–
3
–
2
–
1
–
0
W/R
The HOLD bit enables the Hold pin functionality. It must
be set to a ‘0’ before HOLD pin is brought low for HOLD
MODE MODE
0
0
0
0
1
HOLD
function to work properly. Setting HOLD to ‘ 1 ’ disables
W/R = writable/readable.
feature.
Bits 2 through 5 are reserved and should always be set
to ‘ 0 ’. Bit 1 will read back as ‘ 1 ’ but should always be
written as ‘ 0 ’.
See Figure 2-7 for the RDSR timing sequence.
FIGURE 2-7:
CS
READ STATUS REGISTER TIMING SEQUENCE ( RDSR )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
SI
0
0
0
0
0
1
0
1
High-Impedance
Data from STATUS Register
SO
7
6
5
4
3
2
1
0
DS22126B-page 10
Preliminary
? 2009 Microchip Technology Inc.
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